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Clocking and Power Integrity

Power integrity optimization

SoC clock designers are well aware of the impact of PI degradation on clocking. Clock edge jitter is a direct consequence of transient (or AC) supply noise. DC voltage differences contribute to clock skew variation in different parts of the chip. Clock edge rates also depend on available supply differential [4]. These aspects of clock signal integrity impact both performance and power consumption. But less clear is the converse: the impact of clocking upon power integrity. And its consequence upon chip performance/power.

What is often also unclear is the attribute of PI degradation that has the most impact on chip performance. Is it Droop, a transient response of a power grid segment to a current stimulus? Or Drop, a static (or averaged) counterpart? Or a vector combination? How, where, and when do these aspects impact IP block/chip function? And what measure of PI degradation must a chip/IP Block designer pay careful attention to?

A decade ago, we looked at this aspect to answer a customer's simple query [1]. Should corner caps, part of an IO Ring on a separate power domain, connect into the core power grid? Figure 1 shows noise simulation results on the chip derived from an old version of PI-FP, a Continuum simulator.

Figure 1: Spatio-temporal power grid noise simulation w/w-o IO Ring corner caps

The chip was a CMOS Clock Generator. Its specific function brought PI degradation and clocking performance into direct conflict. Spatiotemporal simulations in PI-FP [3] showed that though peak chip noise (DVD) reduced by ~10mV with corner caps connecting to the core power grid, noise at clock buffer locations in the chip increased noticably. The decision then involved a tradeoff between hot spot noise amplitude and increased spread of noise.

In 'PI Continuum Simulation: Load modulation,' we explored the PI impact of clock-domain splitting. A simplistic two-domain example indicated a potential for increased noise. This article looks at clock edge dither that modulates load currents. We investigate the PI impact of more load current envelopes at constant power consumption.

What Droop, Drop, or Spatial Noise Distribution, is critical PI degradation?

"It depends!" is a simple and evasive answer [2].

Yet depends it does. Simple experiments on arrays of logic gates show that delay differences depend on the average supply voltage level, and are largely independent of noise waveform shape [4]. The integral of noise is thus an important measure. But peak noise during data transitions can cause races, hazards, and metastability. Such noise can lead to incorrect data capture or even data bit flips. Average noise levels over memory arrays, often a large part of SoC's, may have little to no effect. Substrate noise injection, determined by capacitance ratios, relates to the transient content, not the average level. Clock and data jitter are also transient-noise related.

Visual, spatiotemporal, dynamic views of PI degradation help, more so than dry matrices of abstract numbers. Figures 2 and 3 illustrate the results of controlled clock edge dither and snapshots of corresponding power grid noise captured at its peak. The simulation model and environment are the same as the Load Modulation experiment referred to above.

Figure 2: Block load current wave shapes produced by clock dither design

Figure 3: Power grid noise droop and distribution w/ load modulation


Discussion: Peak, Average, and Spatiotemporal Distribution of Noise

In a recent Planet Analog® article, Non-Correlation of Peak Noise and Peak Current, we saw that noise maxima often do not correlate with load current peaks. A complex combination of noise components in a holistic (or HOLONOMIC as Cadence Design Systems® described Anasim's PI methodology, including it in slide 10 without permission or attribution) chip PDN ensures this behavior. We see the same in continuum simulation results shown in Figures 2 and 3. The Gaussian and Triangular load current waves have the same peak load current value, but the corresponding peak noise values, in a true physical simulation, are rather different.

Sure, as we change clock edge placement design, load current waves and peak noise change. Some distributions generate the least peak noise. But is that all that matters? Noise over an IP Block isn't a one-dimensional v(t) curve spread out over the block area. As we see in Figure 3, noise changes in x, y, and t. The largest peak doesn't show the most widespread noise. When you push down on hot spots, you may well be pushing noise up at some other place - or time.

That makes intuitive sense, no? A given IP Block has a certain number of actions to complete in a clock cycle. A fixed number of transitions, a finite amount of charge to transfer. The ΔQ doesn't change, unless one changes the voltage, circuits, or data. Averaged over the block area capacitance, this ΔQ produces a finite ΔV. But how this charge flows into and out of the area, or δQ/δx, δQ/δy, and δQ/δt, does impact noise. Slower - or more spread out - transitions can see lower PDN impedance to charge flow. And, lower, more widespread noise as in the Half-Sine load wave case.

The Bathtub load wave case is interesting in that it generated lower noise and spread in this simulation. Though this load wave resembles the dual-peak case, peak noise has shifted in time to the first load peak. Thus the observed noise peaking phenomenon is different from that of the dual-peak simulation. The Gaussian load wave, a default assumption for clock edge distribution, looked the least desirable in this true-physical PI exploration.

But what of average noise, which we've seen to matter most for simple logic gate delays? Here, as in my Clock Generator chip case, noise over critical circuit areas may be of key importance. High-performance logic, clock buffers, and critical circuit paths may merit careful inspection. Memory and decoupling capacitance regions may need less scrutiny. An Area Integral of noise over a chosen duration can provide a measure of such average.

A spatiotemporal, true physical simulator generating numerical area-based results is ideal for such Area Integral power integrity measurement. True physical analyses incorporate droops and overshoots, and wave propagation, and thus provide accurate measures of noise. Besides, chip, package, and system-level effects combine in a holistic PDN model. Spatial awareness in the simulator simplifies calculating noise averages over sensitive areas. All it takes is post-processing the noise wave data generated.


1) Yes, clocking and clock management design do impact PI Degradation, both Dynamic Voltage Droops and Drop.
2) Based on circuit and chip function, noise spread over critical regions may matter more than DVD hot spots [1].
3) Both transient (Voltage Droop) and average (Voltage Drop) noise measures are important indicators of PI degradation.
4) Spatiotemporal, true physical modeling and simulations provide accurate, advanced insights into PI [3].

This experiment was created and run in a PI-FP GUI, and while simulations took only a few minutes, documentation and presentation required a good few hours. A true-physical 'what-if' environment greatly enhances early design exploration. For more on PI-FP, or such experiments, please contact us.


[1] Raj Nair, Anasim Corp. "IC Floorplanning and Power Integrity," SOCcentral 2010.
[2] Raj Nair and Donald Bennett, Anasim Corp. "Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity," EETimes May 2008.
[3] Raj Nair and Donald Bennett, Anasim Corp. "Power Integrity Analysis and Management for Integrated Circuits," Pearson Education - Prentice Hall, 2010.
[4] M. Hashimoto and Raj Nair, "Power Integrity for Nanoscale Integrated Systems," McGraw Hill, 2014.

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