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Technology Patents and Silicon IP

ComLSI has developed Silicon IP (180nm Logic CMOS) for TMDS and LVDS-compatible CBDS Transceivers and support IP such as a wideband, low-jitter, integer PLL and wideband, high-PSRR linear voltage regulators. These silicon IP Cores implement patented or patent-pending technologies. Additionally, ComLSI has researched and developed power management technologies and IP as described below.

Energy-Efficient Rapid Power MOSFET Switching

ComLSI's Power Management intellectual property includes patented energy-efficient RPTS technology. Capable of SIMULTANEOUS gate-swing and ON-Resistance reduction, this power transistor bias and drive technique reduces switching AND conduction losses in DC-to-DC converters and related applications. It is believed to be the only circuit solution applicable to significantly reducing power transistor losses in switched converters. click on 'RPTS' above for a presentation on its benefits.

'True-Differential' Class-B Differential Signaling (CBDS) Driver

ComLSI's high-speed differential signaling technologies include patented true-differential CBDS Drivers. Capable of either high voltage swings through high current output, or low power through the use of the entire supply current drawn into signal development, this driver is LVDS compatible. Click on 'CBDS' above for more.

Active Packaging

ComLSI's Active Packaging IP includes patented Package-on-Package SAPI or Stacked Active Passive Integration. SAPI is a technology direction combining active circuits, passive elements and packaging. The trend towards smaller, higher performance devices with greater functionality compels integration techniques such as package-on-package or PoP. SAPI takes PoP and System-in-Package techniques a big step further by providing symbiotic functionality within the package that amplifies the utility and performance of a component or system while minimizing substrate real-estate use and cost.

Source-Coupled Differential Signaling (SCDL) Driver/Receiver

ComLSI's high-speed differential signaling technologies include patent-pending fully-differential SCDL for HDMI over 25m cable Drivers & Receivers. The drivers minimize transition energy consumption, undershoots and overshoots while increasing speed through source-coupled drive and provide high-voltage compatibility in receivers. The drivers and receivers are DVI/HDMI compatible, and are additionally suitable for driver and receiver equalization for enhanced multimedia cable range.

SerDes Circuits IP

ComLSI's products in the Serializer-Deserializer area include wide-dynamic range, low-jitter clock extraction and synthesis PLL's, high-speed, high-gain differential receivers, active and passive equalization, and clock and data recovery loops: Pelican IP (180 nm)



ComLSI has developed and patented IP for solutions to the looming Power Integrity Wall such as Active Noise Regulation and Active VLSI Packaging technology (ANR/AVP). Some patents are listed below.


Issued patents and select pending applications
  DC-DC Converter: “Method & apparatus for low input impedance power switch drive”
  Battery Mangmnt: “Method & apparatus for charging, discharging and protection of electronic battery cells”
  Active Regulation: “Voltage droop suppressing active interposer”
  Active Regulation: “Voltage droop suppressing Circuit”
  Active Regulation: “Active Noise Regulator”




“Method & apparatus for low input impedance power switch drive”
USPTO DDP 528845
USPTO Prov. Appl. # 60/460391
Utility appl. 10/794625

This patent protects an optimized driver for JFET or MOSFET power switches that provides greater efficiency, speed and an elimination or reduction in external components such as a resistor and a capacitor used in prior art. It additionally provides the inherent ability to measure the switch current flow as well as the switch temperature allowing for further optimization in the efficiency of the system through PWM frequency and drive signal modulation. Particularly suited for the drive of low-gate-threshold power FET switches from a single driver power supply, this IP steps the cost/performance graph lower in a multi-billion $ market.
Issued Patent US 7126387
“Method & apparatus for charging, discharging and protection of electronic battery cells”
USPTO Prov. Appl. no. 60/495835
Utility appl. 10/714,424

This protects a monitor/controller integrated circuit employed with a JFET series-pass switch in a battery pack. Prior art systems require two switch devices in series, approximately quadrupling the silicon area for a given 'ON' resistance. The invention architecture replaces two FETs with a single bi-directional device, and additionally provides a means for accurate current sensing that eliminates prior art external or internally integrated and trimmed precision resistances. It also provides an elegant means for temperature sensing that can eliminate the temperature sensor externally integrated into the battery 'pack'. It also provides a novel method for output short-circuit fault and open state detection that greatly minimizes the value of the timing capacitance employed for a reset time determination, thus enabling a one-chip integrated solution. With a co-packaged switch device that further improves temperature-sensing accuracy, the IP promises a single-component solution for battery packs. While providing a quantum shift in the cost/performance curve, this IP addresses a very high-volume, high-revenue market. Publication
“Voltage droop suppressing active interposer”
US Patent 7291896

A key component of the Active VLSI Packaging architecture, this invention provides a space-optimal, low-cost, symbiotic assembly of high-bandwidth regulation with an SoC. Through an active interposer layer, a package capacitor is converted into a reservoir of charge at high energy that supplies transient needs of a high-performance chip. Employing interconnect parasitic inductance, the active interposer also provides very high-bandwidth, efficient, switched voltage conversion powering voltage islands in multi-core SoC's. Issued US 7291896
“Voltage droop suppressing circuit”
US Patent 7378898

The claims in this application protect a novel circuit and component integration architecture that addresses and minimizes voltage droops occurring on high-performance VLSI component power grids. While enhancing 'power integrity', the invention actually reduces overall cost by enhancing the effectivity of the package and it's components in minimizing noise. Through active intervention, the invention device shoulders the burden of noise containment and relaxes the requirements on components and systems delivering power. Particularly suited for CPU packages, the invention devices can either reduce cost or enhance performance, providing immediate benefits for all segments of the CPU market.
Issued US 7378898
“Active Noise Regulator”
Utility appl. (patent pending)

The Active Noise Regulator (ANR) is a novel circuit and passive component integration architecture that addresses and minimizes voltage droops and overshoots on high-performance VLSI component power grids. Responding actively to noise, the invention actually reduces overall cost by enhancing the effectivity of the package and its components in minimizing noise. ANR's perform noise suppression efficiently through bidirectional charge transfer into and out of the component power grid. Particularly suited for processor packages, the invention devices can both reduce cost and enhance component performance.

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