Local Charge Reservoirs
The previous lessons established that dynamic voltage droop occurs when a sudden current demand propagates through the power network as a wave, encountering inductive impedance along the way. The droop persists until enough charge arrives from upstream sources to satisfy the load. In a real system, the voltage regulator module on the circuit board may sit 5 to 10 centimeters from the die, and package redistribution layers add further distance. At the speed of signal propagation on a PCB, roughly half the speed of light, a round trip of 10 centimeters takes on the order of a nanosecond. For a workload that switches in hundreds of picoseconds, that nanosecond is an eternity.
Decoupling capacitors address this problem by acting as local charge reservoirs. A capacitor placed near a switching load stores energy in its electric field. When the load draws a sudden current, the capacitor discharges into the load, supplying charge from a short electrical distance rather than from the far-away regulator. The voltage at the load droops less because the effective source impedance seen by the transient is lower. As the disturbance propagates outward and reaches progressively more distant elements of the PDN, those elements begin contributing current as well, and the local capacitor recharges. The decoupling capacitor does not eliminate droop. It reduces the magnitude of droop by shrinking the time window during which the load is electrically isolated from its primary power source.
This picture is appealingly simple, but it conceals an important subtlety. The capacitor is not connected to the load through a perfect wire. There is always some inductance in the current loop between the capacitor and the load, arising from the physical length of the traces, the via transitions, and the capacitor's own internal geometry. That loop inductance determines how quickly charge can flow from the capacitor to the load, and it turns out to be the dominant factor governing decoupling effectiveness.
Loop Inductance Governs Effectiveness
Engineers sometimes fall into the habit of specifying decoupling by total capacitance, adding more microfarads in the hope of reducing noise. This approach misses the point. Consider two capacitors: one rated at 10 nF with a loop inductance of 1 nH to the load, and another rated at 100 nF with a loop inductance of 10 nH. The characteristic impedance of each, given approximately by Z = √(L/C), tells the story. For the first capacitor, Z = √(1 nH / 10 nF) ≈ 0.32 Ω. For the second, Z = √(10 nH / 100 nF) ≈ 0.32 Ω. Despite having ten times less capacitance, the first capacitor presents the same impedance to the load because its lower loop inductance compensates. If the first capacitor had even slightly less loop inductance, say 0.5 nH, its impedance would drop to about 0.22 Ω, making it meaningfully more effective than the larger capacitor.
The resonant frequency of the LC combination also matters. A capacitor is only useful for decoupling at frequencies below its self-resonant frequency, where it still looks capacitive. Above resonance, the parasitic inductance dominates and the component behaves as an inductor, which is the opposite of what is needed. The self-resonant frequency is fres = 1 / (2π√(LC)), so lower inductance not only reduces impedance but also extends the useful frequency range of the capacitor. This is why the physical placement and mounting geometry of a decoupling capacitor often matter more than its nominal capacitance value.
In practical PCB design, this principle drives the preference for small-body capacitors mounted with minimal via transitions and short traces. A 0201-sized MLCC placed directly over a power-ground via pair will outperform a 0805-sized capacitor several millimeters away, even if the latter has far greater nominal capacitance. The routing geometry, the via stub length, the pad dimensions, and the ground return path all contribute to loop inductance. Reducing any of these reduces the impedance seen by the transient and improves decoupling performance.
Three Levels of Decoupling
A modern power delivery network employs decoupling at three distinct physical scales, each addressing a different range of frequencies. The separation arises naturally from the electrical distances involved: a capacitor can only effectively decouple events whose timescale is longer than the round-trip propagation delay between the capacitor and the load.
At the board level, bulk electrolytic and polymer capacitors in the range of tens to hundreds of microfarads handle events on the microsecond timescale. These capacitors are physically large, often several millimeters in body size, and sit centimeters from the die. Their loop inductance to the load is substantial, typically tens of nanohenries, which limits their effectiveness above a few megahertz. They serve primarily to stabilize the supply during slow load transients and to provide a low-impedance path at frequencies where the voltage regulator's output impedance begins to rise. Think of them as the strategic reserve: slow to deploy, but carrying significant energy.
At the package level, multilayer ceramic capacitors in the range of tens to hundreds of nanofarads handle events on the nanosecond timescale. These components are mounted on the package substrate or, in some advanced designs, embedded within it. Their proximity to the die and their compact geometry give them loop inductances on the order of a few hundred picohenries to low single-digit nanohenries. They are effective in the tens to hundreds of megahertz range and form the primary defense against the droop caused by workload-level current transients, such as a processor core waking from clock-gating or a memory controller initiating a burst access.
At the die level, on-chip decoupling capacitors handle the fastest events, those occurring on sub-nanosecond timescales. These are not discrete components but structures fabricated directly in the silicon process: MOS capacitors formed by gate oxide over a well, or metal-insulator-metal (MIM) capacitors built in the back-end metal stack. Their loop inductance to the switching transistors is extraordinarily small, measured in femtohenries to low picohenries, which allows them to respond to current demands that change on the scale of a single clock edge. On-chip decoupling is effective from hundreds of megahertz into the multi-gigahertz range, a frequency band that no external component can reach.
Each level of decoupling takes responsibility for a frequency band, and together they must cover the full spectrum from DC to the highest relevant switching frequency. If any band is left uncovered, the PDN impedance will spike in that range, and any current transient with spectral content in that band will produce an outsized voltage disturbance.
Impedance Targeting Across the Full Bandwidth
The concept of impedance targeting provides the analytical framework for coordinating all three levels of decoupling. The approach begins with a simple requirement: the voltage at the load must remain within a specified tolerance under the worst-case current transient. If the supply voltage is Vdd, the allowed voltage variation is Vdd × margin (where margin might be ±5% or ±3% depending on the process), and the peak transient current is Imax, then the maximum tolerable PDN impedance at any frequency is Ztarget = (Vdd × margin) / Imax. For a 0.8 V supply with 5% margin and a 100 A peak transient, Ztarget is 0.4 mΩ. This is a stringent number, and meeting it across the full bandwidth from DC to several gigahertz is the central challenge of PDN design.
The impedance profile of a well-designed PDN looks approximately flat when plotted on a log-frequency axis, hovering at or below Ztarget across the entire range. At the lowest frequencies, the voltage regulator holds the impedance down through its feedback loop. As frequency rises beyond the regulator's bandwidth, typically in the low kilohertz range, bulk board capacitors take over and keep the impedance below the target. Higher still, package-level MLCCs maintain the impedance through the megahertz range. At the highest frequencies, on-chip decoupling provides the final coverage.
The transitions between these regions are where problems tend to arise. The anti-resonance between the inductance of one decoupling stage and the capacitance of the next can produce impedance peaks that exceed the target. Managing these anti-resonances requires careful selection of capacitor values, deliberate spreading of resonant frequencies across multiple components, and attention to the parasitic inductance at each stage. In some designs, resistive damping is intentionally introduced, either through capacitor ESR or through explicit resistive elements, to flatten the impedance peaks at transition frequencies. The goal is not to minimize impedance at every point, which would be wasteful, but to keep it reliably below the target everywhere.
On-Chip Decoupling and the Area Trade-off
On-chip decoupling occupies a unique position in the hierarchy because it is the only option for the fastest transients and because it competes directly with logic for die area. Unlike board and package capacitors, which are external components added to the bill of materials, on-chip decoupling consumes silicon real estate that could otherwise hold functional transistors. This creates a direct tension between power integrity and computational density.
The placement of on-chip decoupling is as important as its quantity. A decoupling cell on the far side of the die from a heavily switching logic block provides little benefit, because the on-chip power grid introduces its own resistance and inductance over millimeter-scale distances. Effective on-chip decoupling must be distributed near the loads it serves, ideally interleaved with the logic cells in the standard-cell rows or placed in dedicated decap fill regions adjacent to high-activity blocks. Physical and electrical proximity are both required.
Process scaling offers some relief. As transistor dimensions shrink, the capacitance per unit area of MOS and MIM structures increases because the dielectric thickness decreases while the dielectric constant may improve. The capacitance density (CA) in advanced nodes can reach tens of femtofarads per square micrometer, which is substantially higher than older processes. However, the benefit is partial at best. The same scaling that increases capacitance density also increases current density and switching speed, driving up di/dt faster than the available decoupling can compensate. Each new process node tends to make the power integrity problem harder, not easier, despite the improved CA.
The allocation of die area to decoupling is therefore a design optimization problem, not a simple rule of thumb. Too little on-chip decoupling and the supply voltage violates its margin during fast transients, causing timing failures or functional errors. Too much decoupling and the die grows larger than necessary, increasing cost and reducing the number of good dies per wafer. A power-integrity-aware floorplanner must evaluate the noise profile of each region of the chip, understand the switching activity patterns of the workload, and distribute decoupling where it delivers the greatest reduction in peak impedance per unit of consumed area.
Toward Impedance-Aware Design
The principles of decoupling and impedance targeting together define a methodology that connects circuit-board layout, package design, and silicon floorplanning into a unified optimization problem. Each level of the physical hierarchy owns a frequency band, and the aggregate impedance profile must satisfy a single target derived from the voltage margin and current specifications. Failures in any one band propagate as voltage noise into the others, because anti-resonances and reflections couple the stages together.
In practice, achieving a flat impedance profile requires simulation across the full bandwidth, with accurate models for every component in the PDN, from the VRM output filter through the board planes, through the package substrate, and into the on-chip power grid. The models must capture not only the self-impedance of each element but also the mutual coupling between adjacent planes and the distributed nature of the on-chip grid. Lumped-element models suffice at low frequencies, but at the multi-gigahertz range where on-chip decoupling operates, distributed electromagnetic models become necessary.
The lessons so far have built a picture of the PDN as a physical system governed by wave propagation, inductive and resistive losses, and transient current demands. Decoupling capacitance is the primary tool for managing the dynamic behavior of that system. Its deployment is constrained by geometry, by loop inductance, by process technology, and by the economics of die area. The next lesson will examine how these constraints interact in real design scenarios, where multiple noise sources operate simultaneously and the PDN must satisfy all of them at once.