Tag Archives: resonance

PI discussion on LinkedIn(tm)

Anasim co-founder Raj Nair discusses PI and related challenges in semiconductor scaling and chip/system design in a LinkedIn(tm) discussion forum Power Integrity and Energy Management for Semiconductor Components.

As anticipated in the online white paper A Power Integrity Wall Follows the Power Wall! published more than 5 years ago, PI has risen in dominance to become a critical challenge for SoC’s in the ULSI and 3D integration era.

Join the ongoing PI discussion on LinkedIn’s professional discussion forum above.

Total Power Integrity

Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity PDF download

“Power integrity analyses in SoC’s is hence moving from traditional IR Drop to total power integrity, and true-electromagnetic simulations, comprehending all aspects of interactions between integrated circuit blocks and the common power delivery network.”

Anasim Power Integrity Aware Methodology

A power-integrity-aware physical design methodology enables front-end optimization of power grid metal resource usage, decoupling capacitance planning and placement, and significantly relaxes routing constraints.

Power-Integrity (PI) aware ULSI design flow

Power-Integrity (PI) aware ULSI design flow

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