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Continuum (Analog) Analysis for Power Integrity

Raj — Sat, 12 Jun 2010 21:27:35 +0000

June 2010: Power Integrity (PI) analysis has traditionally been conducted using lumped, discrete elements and circuits, which lead to exponential simulation complexity, approximate models, and often, inaccurate results. In continuum-models based analysis, a chip power grid and distribution network is modeled as a continuous surface, employing distributed models for circuits and capacitance. This not only eliminates the exploding computational complexity for PI analysis in nanoscale chips, it facilitates physical, true-electromagnetic simulations for chips, packages, and 3D assemblies. Continuum-models based analysis is “analog” in the sense that a layer to be analyzed is treated as a spatial potential or voltage continuum, similar to analog signals being time-continuous in nature, as opposed to analyzing discrete elements and their interactions.

Read more on this in a SOCcentral featured article. A comprehensive treatment of Continuum Modeling is accessible in Anasim’s PI book for IC’s.

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Simulation speed and accuracy

Raj — Sun, 05 Jul 2009 16:11:36 +0000

As simulation complexity in the number of elements explodes in the nanoscale regime (sub-100nm), tools face a difficult choice in reducing simulation times, where model accuracy is compromised. Tools employing model simplifications commonly claim 5% SPICE accuracy, or worse, which consumes design margin available for power integrity, and adds uncertainty. Besides, model simplification with large numbers of interacting inductors and capacitors is a complex task.

pi-fp, with continuum modeling, and distributed electrical parameters, load, and capacitance modeling, does not compromise simulation accuracy for speed, but reduces simulation resolution instead. By increasing the unit area simulated, from 50u by 50u to 100u by 100u, simulation speed in pi-fp is enhanced by at least a factor of 4, with no loss of grid voltage variation accuracy.

For more information: pi-fp brochure

Active Noise Regulation

Raj — Tue, 19 May 2009 18:29:06 +0000

“Yield loss and timing problems undetected by traditional verification and validation methods can be traced to a significant decrease in supply noise margin in components using advanced fabrication processes at and below the 90nm node. A combination of increased current density at lower supply voltages and supply pathway impedance results in large, on and off chip, relative supply variations called voltage droops. These fluctuations make it more difficult to reduce static and dynamic power and energy consumption by further reductions in supply voltage, despite the scaling direction for semiconductors…”

Read more on how active noise regulation helps minimize power and energy consumption through noise minimization here (HTML).

Total Power Integrity

Raj — Sat, 16 May 2009 00:29:55 +0000

Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity PDF download

“Power integrity analyses in SoC’s is hence moving from traditional IR Drop to total power integrity, and true-electromagnetic simulations, comprehending all aspects of interactions between integrated circuit blocks and the common power delivery network.”

Power Integrity Wall

Raj — Sat, 16 May 2009 00:24:14 +0000

A Power Integrity Wall follows the Power Wall: PDF download

“Today, power consumption is the single dominant design constraint for integrated circuits, but less noticed, and even less respected, is power integrity, despite its undeniable role in determining power and energy consumption.”

Download the PDF to read further…

Roof Planning

Raj — Sat, 16 May 2009 00:18:39 +0000

Power Integrity and Energy Aware Floorplanning: PDF download

“We have heard so much about floorplanning for integrated circuits – routing, timing awareness, even leakage and temperature awareness; how often do we come across the term ‘Roof Planning’ in SoC’s?”

Download the article PDF to read on…

Anasim Power Integrity Aware Methodology

Prathik Raj — Sat, 11 Apr 2009 16:33:27 +0000

A power-integrity-aware physical design methodology enables front-end optimization of power grid metal resource usage, decoupling capacitance planning and placement, and significantly relaxes routing constraints.

Power-Integrity (PI) aware ULSI design flow

Click to enlarge image