Anasim

August 2010: Early PI-aware design is a significant aspect of IC floorplanning, particularly in nanoscale systems where low power/energy and efficient use of chip/pkg metal and decoupling resources are key design constraints. The advent of 3D integration in the form of chip or package stacking makes early front-end analysis of PI through high levels of abstraction and physics-based simulations all the more necessary. Correlation between PI and thermal issues provides an added benefit in front-end PI analysis and optimization…

Continue reading in an SOCcentral featured article. More on power integrity and floorplanning: Anasim’s PI book for IC’s.

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Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity PDF download

“Power integrity analyses in SoC’s is hence moving from traditional IR Drop to total power integrity, and true-electromagnetic simulations, comprehending all aspects of interactions between integrated circuit blocks and the common power delivery network.”

Power Integrity and Energy Aware Floorplanning: PDF download

“We have heard so much about floorplanning for integrated circuits – routing, timing awareness, even leakage and temperature awareness; how often do we come across the term ‘Roof Planning’ in SoC’s?”

Download the article PDF to read on…

RLCSim is a Windows(tm) executable that performs noise analysis on a power grid over a circuit block. This tool, a pre-cursor of pi-fp, considers grid resistance (IR drop), inductance (L*di/dt) or voltage droop, and distributed capacitance that absorbs transients, and displays noise propagation and summing within the block.

Inputs include grid parameters, block power consumption profiles and capacitance.

FREE RLCSim Windows(tm) ZIP Download

Shown below is a noise simulation result using RLCSIM demonstrating detrimental effects of lens-shaped on-chip decoupling capacitance structure. Power grid noise from an on-chip source is focused behind the capacitance structure, illustrating distributed true-electromagnetic simulation capability absent in other power integrity analysis tools.

Download a full-size version of the animation here

Download/View (PDF): Effective Current Density.pdf

A power-integrity-aware physical design methodology enables front-end optimization of power grid metal resource usage, decoupling capacitance planning and placement, and significantly relaxes routing constraints.

Power-Integrity (PI) aware ULSI design flow

Click to enlarge image