Anasim

August 2010: Early PI-aware design is a significant aspect of IC floorplanning, particularly in nanoscale systems where low power/energy and efficient use of chip/pkg metal and decoupling resources are key design constraints. The advent of 3D integration in the form of chip or package stacking makes early front-end analysis of PI through high levels of abstraction and physics-based simulations all the more necessary. Correlation between PI and thermal issues provides an added benefit in front-end PI analysis and optimization…

Continue reading in an SOCcentral featured article. More on power integrity and floorplanning: Anasim’s PI book for IC’s.

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June 2010: Power Integrity (PI) analysis has traditionally been conducted using lumped, discrete elements and circuits, which lead to exponential simulation complexity, approximate models, and often, inaccurate results. In continuum-models based analysis, a chip power grid and distribution network is modeled as a continuous surface, employing distributed models for circuits and capacitance. This not only eliminates the exploding computational complexity for PI analysis in nanoscale chips, it facilitates physical, true-electromagnetic simulations for chips, packages, and 3D assemblies. Continuum-models based analysis is “analog” in the sense that a layer to be analyzed is treated as a spatial potential or voltage continuum, similar to analog signals being time-continuous in nature, as opposed to analyzing discrete elements and their interactions.

Read more on this in a SOCcentral featured article. A comprehensive treatment of Continuum Modeling is accessible in Anasim’s PI book for IC’s.

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Power Integrity and Energy Aware Floorplanning: PDF download

“We have heard so much about floorplanning for integrated circuits – routing, timing awareness, even leakage and temperature awareness; how often do we come across the term ‘Roof Planning’ in SoC’s?”

Download the article PDF to read on…

A power-integrity-aware physical design methodology enables front-end optimization of power grid metal resource usage, decoupling capacitance planning and placement, and significantly relaxes routing constraints.

Power-Integrity (PI) aware ULSI design flow

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