Anasim » Floorplanning http://www.anasim.com Your Total Power Integrity Team Tue, 03 Aug 2010 20:12:09 +0000 http://wordpress.org/?v=2.9.1 en hourly 1 IC Floorplanning and Power Integrity http://www.anasim.com/general/ic-floorplanning-and-power-integrity/ http://www.anasim.com/general/ic-floorplanning-and-power-integrity/#comments Tue, 03 Aug 2010 20:12:09 +0000 Raj http://www.anasim.com/?p=207 August 2010: Early PI-aware design is a significant aspect of IC floorplanning, particularly in nanoscale systems where low power/energy and efficient use of chip/pkg metal and decoupling resources are key design constraints. The advent of 3D integration in the form of chip or package stacking makes early front-end analysis of PI through high levels of abstraction and physics-based simulations all the more necessary. Correlation between PI and thermal issues provides an added benefit in front-end PI analysis and optimization…

Continue reading in an SOCcentral featured article. More on power integrity and floorplanning: Anasim’s PI book for IC’s.

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]]> http://www.anasim.com/general/ic-floorplanning-and-power-integrity/feed/ 0 Roof Planning http://www.anasim.com/articles/119/ http://www.anasim.com/articles/119/#comments Sat, 16 May 2009 00:18:39 +0000 Raj http://www.anasim.com/?p=119 Power Integrity and Energy Aware Floorplanning: PDF download

“We have heard so much about floorplanning for integrated circuits – routing, timing awareness, even leakage and temperature awareness; how often do we come across the term ‘Roof Planning’ in SoC’s?”

Download the article PDF to read on…

]]> http://www.anasim.com/articles/119/feed/ 0 Anasim Power Integrity Aware Methodology http://www.anasim.com/methodology/anasim-power-integrity-aware-methodology/ http://www.anasim.com/methodology/anasim-power-integrity-aware-methodology/#comments Sat, 11 Apr 2009 16:33:27 +0000 Prathik Raj http://www.anasim.com/?p=19 A power-integrity-aware physical design methodology enables front-end optimization of power grid metal resource usage, decoupling capacitance planning and placement, and significantly relaxes routing constraints.

Power-Integrity (PI) aware ULSI design flow

Power-Integrity (PI) aware ULSI design flow

Click to enlarge image

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