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	<title>Anasim &#187; energy</title>
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	<description>Your Total Power Integrity Team</description>
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		<title>Power Integrity Wall</title>
		<link>http://www.anasim.com/articles/121/</link>
		<comments>http://www.anasim.com/articles/121/#comments</comments>
		<pubDate>Sat, 16 May 2009 00:24:14 +0000</pubDate>
		<dc:creator>Raj</dc:creator>
				<category><![CDATA[Articles]]></category>
		<category><![CDATA[design]]></category>
		<category><![CDATA[energy]]></category>
		<category><![CDATA[noise]]></category>
		<category><![CDATA[power]]></category>
		<category><![CDATA[power integrity]]></category>
		<category><![CDATA[power integrity wall]]></category>
		<category><![CDATA[power wall]]></category>
		<category><![CDATA[scaling]]></category>
		<category><![CDATA[SoC]]></category>
		<category><![CDATA[wall]]></category>

		<guid isPermaLink="false">http://www.anasim.com/?p=121</guid>
		<description><![CDATA[A Power Integrity Wall follows the Power Wall: PDF download
&#8220;Today, power consumption is the single dominant design constraint for integrated circuits, but less noticed, and even less respected, is power integrity, despite its undeniable role in determining power and energy consumption.&#8221;
Download the PDF to read further&#8230;
]]></description>
			<content:encoded><![CDATA[<p><strong>A Power Integrity Wall follows the Power Wall</strong>: <a href="http://www.anasim.com/papers/pifp2.pdf">PDF download</a></p>
<p>&#8220;Today, power consumption is the single dominant design constraint for integrated circuits, but less noticed, and even less respected, is power integrity, despite its undeniable role in determining power and energy consumption.&#8221;</p>
<p>Download the PDF to read further&#8230;</p>
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		<title>Anasim Power Integrity Aware Methodology</title>
		<link>http://www.anasim.com/methodology/anasim-power-integrity-aware-methodology/</link>
		<comments>http://www.anasim.com/methodology/anasim-power-integrity-aware-methodology/#comments</comments>
		<pubDate>Sat, 11 Apr 2009 16:33:27 +0000</pubDate>
		<dc:creator>Prathik Raj</dc:creator>
				<category><![CDATA[Methodology]]></category>
		<category><![CDATA[Anasim]]></category>
		<category><![CDATA[Design Methodology]]></category>
		<category><![CDATA[effective current density]]></category>
		<category><![CDATA[efficiency]]></category>
		<category><![CDATA[energy]]></category>
		<category><![CDATA[Floorplanning]]></category>
		<category><![CDATA[front end optimization]]></category>
		<category><![CDATA[grid]]></category>
		<category><![CDATA[grid simulation]]></category>
		<category><![CDATA[IC Design]]></category>
		<category><![CDATA[L*di/dt]]></category>
		<category><![CDATA[layout]]></category>
		<category><![CDATA[noise]]></category>
		<category><![CDATA[physical design]]></category>
		<category><![CDATA[power]]></category>
		<category><![CDATA[power aware]]></category>
		<category><![CDATA[power grid]]></category>
		<category><![CDATA[power integrity]]></category>
		<category><![CDATA[power integrity aware]]></category>
		<category><![CDATA[resonance]]></category>
		<category><![CDATA[simulation]]></category>
		<category><![CDATA[Software]]></category>
		<category><![CDATA[technology]]></category>

		<guid isPermaLink="false">http://www.anasim.com/?p=19</guid>
		<description><![CDATA[A power-integrity-aware physical design methodology enables front-end optimization of power grid metal resource usage, decoupling capacitance planning and placement, and significantly relaxes routing constraints.
Click to enlarge image
]]></description>
			<content:encoded><![CDATA[<p>A power-integrity-aware physical design methodology enables front-end optimization of power grid metal resource usage, decoupling capacitance planning and placement, and significantly relaxes routing constraints.</p>
<div id="attachment_72" class="wp-caption aligncenter" style="width: 610px"><a href="http://www.anasim.com/wp-content/uploads/2009/04/flow2.gif"><img class="size-medium wp-image-72" title="PI-FP Physical Design Methodology" src="http://www.anasim.com/wp-content/uploads/2009/04/flow2-600x571.gif" alt="Power-Integrity (PI) aware ULSI design flow" width="600" height="571" /></a><p class="wp-caption-text">Power-Integrity (PI) aware ULSI design flow</p></div>
<p>Click to enlarge image</p>
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