Anasim

“Yield loss and timing problems undetected by traditional verification and validation methods can be traced to a significant decrease in supply noise margin in components using advanced fabrication processes at and below the 90nm node. A combination of increased current density at lower supply voltages and supply pathway impedance results in large, on and off chip, relative supply variations called voltage droops. These fluctuations make it more difficult to reduce static and dynamic power and energy consumption by further reductions in supply voltage, despite the scaling direction for semiconductors…”

Read more on how active noise regulation helps minimize power and energy consumption through noise minimization here (HTML).