Dynamic Voltage Droop & Total Power Integrity
May 23, 2008: Anasim founder Raj Nair introduces Total Power Integrity for SoC/SiP designs in an EETimes® article publication Dynamic Voltage Droops and Total Power Integrity. This article is also available in HTML form here.
The article defines and explores ‘total power integrity’ as true-electromagnetic analysis of interactions of load current profiles with power network impedance on an integrated circuit or system.
For far too long, the EDA industry has obscured comprehensive noise analysis including L*di/dt, noise wave propagation and resonant effects by dismissing on-chip inductance as irrelevant to power integrity. In nanoscale processes, where edge rates are at or below 100ps, noise frequencies are 5 GHz or greater with noise waves dissipating inside a chip before they ever reach package leads. In other words, dynamic noise or L*di/dt is determined largely within the chip, and not as much by package inductance that is shielded from these high-frequency noise waves by on-chip capacitance and resistance.
Most articles from the industry continue to talk, even today, only about package inductance as the principal determinant of on-chip dynamic noise. Anasim believes this to be a myth leading us headlong into the Power Integrity Wall. Are ripples in a lake caused only by obstruction in the channels that feed it?
For more information, please contact Enquiries @Anasim .com.
Tags: floorplanning, IR Drop, noise, noise propagation, Power Grid, power integrity, resonance, total power integrity, voltage droop
Beyond IR Drop: Total Power Integrity
May 22, 2007: Anasim’s latest white paper, “Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity” has been published as a feature article at SOCcentral. This paper details the theoretical foundation underlying Total Power Integrity (TPI) analyses that are essential to ‘correct by construction’ nanoscale IC floorplans.
For comments and more information, please write to Enquiries @anasim .com
Tags: dynamic voltage droop, energy, floorplanning, IR Drop, pi-fp, pie-fp, power, power integrity, total power integrity, voltage droop
Beyond IR Drop: Total Power Integrity
Our next article on Power Integrity explores the power supply noise analysis landscape beyond traditional IR Drop.
Revealing theoretical and scaling aspects of Dynamic Voltage Droop (called L*di/dt in the literature), we define Total Power Integrity analysis as the exploration of all forms of power supply variability, and discuss how such analysis may be conducted very early in the design cycle, enabling first-time-right floorplan optimization for SoC’s.
Access this paper here in html and PDF. The article is also due for publication in leading online journals for SoC and EDA.
Please address questions or comments to Enquiries @anasim .com.
Tags: Beyond IR Drop, Droop, Integrity, IR Drop, noise, power, power integrity, Supply noise, voltage droop
Second in article series on Power Integrity
Anasim co-founder Raj discusses the looming Power Integrity Wall for Nanoscale CMOS chips in an SOCcentral featured article “A Power Integrity Wall follows the Power Wall!”
The article reveals a trend for progression of on-chip L*di/dt noise in SoC’s scaling into the nanoscale regime that has the potential to cause significant yield spreading in chips and also has, to this point, not been explored comprehensively.
The article may also be accessed in html or PDF here. Please address any comments or questions to enquiries @anasim .com or raj @anasim .com.
Tags: Integrity, power, Power Grid, power integrity, Power Integrity Wall, Power Wall, Scaling, voltage droop
IR Drop: Isn’t it time for change?
It has been about three years since I blogged in VSIA’s pages about the need for advanced clock skew, jitter and power integrity analysis.
Read it here: VSIA post on Advanced Clock, Power Techniques
Since then, SoC’s have marched on to GHz frequencies and power gating, with power consumption becoming the single dominant design constraint.
Yet, we continue to talk about IR Drop in place of Power Integrity (PI) analysis as in a recent online article about power gating.
Isn’t it high time for a change? Can we recognize that resistance is not the only impedance electrons see on power wires?
Author’s comment: An EETimes article of September 2003 by Andrew Yang of Apache Design Solutions pre-dates my blog comments about the need to move beyond IR Drop analyses. Read our recent article about Moving Beyond IR Drop or access it in PDF here.
Please address questions/comments to Enquiries @anasim .com.
Tags: Beyond IR Drop, Integrity, IR Drop, power, power integrity, voltage droop