Anasim’s Effective Current Density (ECD) published
Anasim Corporation / Sept. 25, 2008
Anasim’s principal invention of “effective current density”, or ECD for short, has been published by the United States Patent & Trademarks Office as USPTO Publication 20080221850.
The application of ECD to power grid analysis detaches simulation time complexity from the number of wires in the grid or the number of load and capacitance components connecting to the grid. More importantly, ECD permits true-electromagnetic simulations of chip and package/board power grids including key R, L and C parameters as well as di/dt and resonance effects.
ECD is the core simulation technology in Anasim’s power integrity aware floorplanner pi-fp.
For more information, please contact enquiries @anasim .com.
Tags: Anasim, ECD, effective current density, pi-fp, Power Grid, simulation complexity reduction, true-electromagnetic
Dynamic Voltage Droop & Total Power Integrity
May 23, 2008: Anasim founder Raj Nair introduces Total Power Integrity for SoC/SiP designs in an EETimes® article publication Dynamic Voltage Droops and Total Power Integrity. This article is also available in HTML form here.
The article defines and explores ‘total power integrity’ as true-electromagnetic analysis of interactions of load current profiles with power network impedance on an integrated circuit or system.
For far too long, the EDA industry has obscured comprehensive noise analysis including L*di/dt, noise wave propagation and resonant effects by dismissing on-chip inductance as irrelevant to power integrity. In nanoscale processes, where edge rates are at or below 100ps, noise frequencies are 5 GHz or greater with noise waves dissipating inside a chip before they ever reach package leads. In other words, dynamic noise or L*di/dt is determined largely within the chip, and not as much by package inductance that is shielded from these high-frequency noise waves by on-chip capacitance and resistance.
Most articles from the industry continue to talk, even today, only about package inductance as the principal determinant of on-chip dynamic noise. Anasim believes this to be a myth leading us headlong into the Power Integrity Wall. Are ripples in a lake caused only by obstruction in the channels that feed it?
For more information, please contact Enquiries @Anasim .com.
Tags: floorplanning, IR Drop, noise, noise propagation, Power Grid, power integrity, resonance, total power integrity, voltage droop
Second in article series on Power Integrity
Anasim co-founder Raj discusses the looming Power Integrity Wall for Nanoscale CMOS chips in an SOCcentral featured article “A Power Integrity Wall follows the Power Wall!”
The article reveals a trend for progression of on-chip L*di/dt noise in SoC’s scaling into the nanoscale regime that has the potential to cause significant yield spreading in chips and also has, to this point, not been explored comprehensively.
The article may also be accessed in html or PDF here. Please address any comments or questions to enquiries @anasim .com or raj @anasim .com.
Tags: Integrity, power, Power Grid, power integrity, Power Integrity Wall, Power Wall, Scaling, voltage droop