Dynamic Voltage Droop & Total Power Integrity
May 23, 2008: Anasim founder Raj Nair introduces Total Power Integrity for SoC/SiP designs in an EETimes® article publication Dynamic Voltage Droops and Total Power Integrity. This article is also available in HTML form here.
The article defines and explores ‘total power integrity’ as true-electromagnetic analysis of interactions of load current profiles with power network impedance on an integrated circuit or system.
For far too long, the EDA industry has obscured comprehensive noise analysis including L*di/dt, noise wave propagation and resonant effects by dismissing on-chip inductance as irrelevant to power integrity. In nanoscale processes, where edge rates are at or below 100ps, noise frequencies are 5 GHz or greater with noise waves dissipating inside a chip before they ever reach package leads. In other words, dynamic noise or L*di/dt is determined largely within the chip, and not as much by package inductance that is shielded from these high-frequency noise waves by on-chip capacitance and resistance.
Most articles from the industry continue to talk, even today, only about package inductance as the principal determinant of on-chip dynamic noise. Anasim believes this to be a myth leading us headlong into the Power Integrity Wall. Are ripples in a lake caused only by obstruction in the channels that feed it?
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Tags: floorplanning, IR Drop, noise, noise propagation, Power Grid, power integrity, resonance, total power integrity, voltage droop