Design Flow & Benefits
Publications
- π-fp to HSpice Correlation report
- Beyond IR Drop: Dynamic Voltage Droops & Total Power Integrity
- A Power Integrity Wall follows the Power Wall! (PDF)
- Power Integrity and Energy aware SoC Floorplanning (PDF)
- Analyzing inductive noise in power grids
- How to dynamically mitigate SoC power supply noise
News / Blog
Read about the latest developments in Anasim.
π-fp Licensing Options
Eval, Monthly, Annual, Perennial
Downloads
- Free DEMO π-fp Simulator for Linux (1MB file)
- Free DEMO π-fp for Windows® & instructions (25MB file)
- π-fp Brochure
- Anasim mutual NDA
- NanoTech 2008 Presentation
- White Papers pifp1.pdf, pifp2.pdf, pifp3.pdf
Power Integrity and Energy aware Floor Planner :π-fp
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Simulation results on a chip with two current source loads at two corners of the chip. In the corner to the left, an 'Active Noise Regulator' interacts with on-chip noise to reduce the voltage droop by about 40%. Multiple simulation output views from π-fp have been combined to provide this animated image. π-fp differentiates itself in being able to conduct 'true dynamic' EM simulations on entire power delivery systems, providing floor planners with the ability to conduct rapid 'what-if' analyses. |
Power grid noise simulation with Active Noise Regulation |
π-fp completes power integrity investigations for SoC floor plans including all essential components such as dynamic, distributed on-chip power consumption, distributed on-chip capacitance, grid and package inductances, package capacitors and power delivery connections in minutes. π-fp permits designers' investigations of grid L*di/dt noise, grid noise propagation and summation, and power delivery system resonances.